This invention relates to a charge transfer device, and more particularly to an input part in the charge transfer device.
An input part in a conventional buried-channel type charge transfer device includes a semiconductor substrate of a first conductivity type, a diffusion region of a second conductivity type formed in a surface portion of the substrate, a first gate electrode hereinafter referred to as a third gate electrode provided on the semiconductor substrate close to the diffusion region, a second gate electrode provided on the semiconductor substrate close to the first gate electrode, and third gate electrode hereinafter referred to as a transfer gate electrode, provided on the semiconductor substrate close to the second gate electrode but far from the first gate electrode. The second gate electrode consists of only a single layer electrode which is usually different from the layer forming the first and third gate electrodes. Since the dimension of this single layer electrode, which determines the amount of charges to be introduced into the charge transfer device, is apt to be affected by manufacturing errors such as under- or over-etching of the electrode material, the accuracy of the charge injection rate depends on the accuracy of the dimension of the second gate electrode.
First, a conventional charge transfer device will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a plan view of the portion of a conventional charge transfer device which is in the vicinity of an input part therein, and FIG. 2 a sectional view taken along the line A-A' in FIG. 1. A diffusion region 1 formed on a P-type semiconductor substrate 4 is an N-type region, and is connected to a wiring layer 2 of aluminum through a connecting portion 2'. This diffusion region 1 serves as a charge injection region, to which an electrical potential is applied from the outside through the wiring 2. A first gate electrode 11 is formed on the substrate via an insulating oxide film 5 so that its one side may be aligned with one side of the diffusion region 1. A second gate electrode 21 is formed in the oxide film 5 close to the first gate electrode 11, and third gate electrodes 31, 32 close to the second gate electrode 21, the electrode 31 comprising a transfer gate electrode. The third gate electrodes 31, 32 are connected to each other through a connecting portion 30 so as to function as a single electrode. Reference numeral 12 denotes an aluminum wiring for the first electrode 11, and 23 an aluminum wiring for the second gate electrode 21. The third gate electrodes 31, 32 are commonly connected via wiring 53 to a clock signal of a shift register operating in a charge transfer manner. Electrodes 41 and 42; and electrodes 51 and 52 of the shift register are connected to each other via connecting portions 40, 50, respectively, to form transfer gate electrodes of the shift register and these electrodes are connected to clock wires 43, 53. In this example, 2-phase clocks are applied through the wirings 43 and 53, respectively. Reference numeral 3 denotes a channel region in which charges are transferred. The electrodes 21, 32, 42, 52 which are shown in broken line in FIG. 1 are made of a first polysilicon layer formed on the oxide film 5, while the electrodes 11, 31, 41, 51, which are shown in solid line in the same figure, are made of a second polysilicon layer formed in a step after the formation of the first polysilicon layer.
The cross-sectional construction of this example will be described in detail with reference to FIG. 2. The polysilicon electrodes 11, 21, 31, 32, 41, 42, 51, 52 are formed on the P-type semiconductor substrate 4 via the insulating oxide film 5 by two different depositions of polysilicon as mentioned above. The side and upper surface of the electrodes 21, 32, 42, 52 are covered by a thermally oxided film to maintain isolation from the electrodes 11, 31, 41, 51. The charge transfer section has a buried-channel construction, and an N-type region 6 is thus formed on the P-type semiconductor substrate 4. Further, in order to transfer charges in a predetermined direction, P-type regions 7 are formed under the electrodes 41, 51 of the second polysilicon layer.
The injection of charges into the above charge transfer device will now be described in the context of a generally-used potential balancing method. FIG. 3a is a sectional view of an input part including the N-type region 1, the first, second and third gate electrodes G1, G2 and G3 and a part of the N-type channel region 6, and FIGS. 3b-3d are diagrams of electric potential versus time showing the steps of charge injection according to the potential balancing method. The charge injection operation is begun by making the electric potential at the input N-type region 1 higher than that in a first gate electrode G1. At this time, as shown in FIG. 3b, the charge flows into a potential well under second gate electrode G1. Thereafter, the electric potential at the input N-type region is made lower than that of the first gate electrode G1 to leave charges in the potential well under the second gate electrode G2, as shown in FIG. 3c. The excess charge flows back to the input N-type region 1. Consequently, the amount of charges left in the electric potential well under the second gate electrode G2 corresponds to the difference between the electric potentials under the first and second gate electrodes G1 and G2. These charges are sent to the N-type region 6 of the shift register by lowering the potential under a third gate electrode G3, as shown in FIG. 3d. The charge transfer rate Q can be expressed by the following formula:
Q.alpha. (difference between electric potentials of G1 and G2) x (area of the gate G2).
Here, while the difference between the electric potentials under the gate electrodes G1 and G2 is controlled by externally applied gate voltages, the area of the gate electrode G2 is strongly affected by the inevitable manufacturing errors. In other words, the injection rate Q depends substantially upon the length of the second gate electrode G2, i.e. the length "l" of the channel under the second gate electrode G2 shown in FIG. 3a, and the channel length "l" under the second gate G2 varies with the etching conditions in the manufacturing of the second gate G2. More particularly, in case of over-etching, the length "l" becomes shorter, and in case of under-etching, the length "l" becomes longer. It is difficult, especially in a wet etching process, to control the etching precisely. Therefore, the channel length "l" under the second gate G2 cannot be precisely controlled. Particularly, when the second gate electrode G2 is formed in a fine pattern, it is convenient to use a smaller channel length "l". However, as the channel length "l" is shortened, the percentage variation due to manufacturing errors becomes longer. As described above, the conventional charge transfer device has a disadvantage that the charge transfer rate is greatly influenced by the channel length "l" of channel under the second gate electrode G2. A charge transfer device which can precisely control the rate of charge injection has been strongly desired, because the injection rate is an important feature of the charge transfer device. While the operation has been explained above in the context of the potential balancing method, the deviation of the charge injection rate in the diode cut-off method similarly depends on the area of the channel under the second gate G2.